Semiconductor chip having via electrodes and stacked semiconductor chips interconnected by the via electrodes

ABSTRACT

A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2008-0104986, filed on Oct. 24, 2008, in the KoreanIntellectual Property Office, the entire content of which isincorporated by reference herein.

BACKGROUND

1. Technical Field

The present disclosure relates to semiconductor devices, and, moreparticularly, to via electrodes for semiconductor chips and stackedsemiconductor chips interconnected by the via electrodes.

2. Discussion of Related Art

As electronic devices become smaller and smaller the use of wire andsolder balls are becoming less and less common. In recent years thesemiconductor industry has been striving to cost effectively producereliable electrically connectable stacks of semiconductor wafers whileminimizing manufacturing difficulties.

In the manufacturing of integrated circuit (IC) devices, components andmetal circuit lines separated by dielectric substrate material, such assilicon oxide, are typically connected through holes or “vias” whichhave been etched through the dielectric substrate material. The throughsilicon via (TSV) is cleaned of photoresist and etch residues and thenfilled with conductive metal to provide an electrical connection fromone side of the substrate to the other.

However, one difficulty that can affect interconnect performance andreliability is when the TSVs are not free of cleaning residue prior tobeing filled. The removal of such cleaning residue, often called “viaveils”, can become difficult because of etch chemistries and may involvethe costly and delicate use of aggressive wet chemical solvents toinsure clean TSVs that provide reliable electrode connection paths whenfilled. Strides have been made to minimize this difficulty through theuse of a dry de-veiling process rather than the aggressive wet solventprocess.

Further, wafer stack packaging (WSP) technology using a TSV as a throughhole electrode for multiple layer packaging continues to be used in anattempt to reduce package thickness, size and interconnection lengthbetween semiconductor chips/dies.

However, because integration density of semiconductor chips isincreasing, the diameters of via holes for forming a conventional TSVare getting smaller. Because an aspect ratio of the hole then becomesvery high, voids may be developed in the via hole during filling thehole with conductive material for forming TSV electrode. Such voidsprecipitate the inducing of a connection failure from one side of thechip to the other, or between dies in the stack.

In an attempt to avoid connection failures, U.S. Patent Publication No.2008/0092378 proposes a method for manufacturing an electroconductivematerial-filled through hole substrate of which the front side and backside are electrically conductive to each other through anelectroconductive material filled into the through holes. Anelectroconductive base layer is formed on one side of a core substratehaving through holes. The through holes are filled with anelectroconductive copper material by electroplating using theelectroconductive base layer as a seed layer. However, the disclosuredoes not address the problem of potential voids in TSVs. Holes in thesubstrate are merely filled and the substrate stripped off and polisheduntil the electroconductive material in the holes is exposed.

In a further attempt to address connections involved in the stacking ofsemiconductor chips, U.S. Pat. No. 6,809,421 proposes a multichipsemiconductor device having a stack of chips each having a semiconductorsubstrate which has a surface on which circuit components are formed.While providing for metal plugs as electrodes through the respectivesubstrates, the disclosure also does not address the problem ofpotential voids in TSVs. Holes in the substrate are merely filled andthe substrate stripped off and polished until the metal plug is exposed.

Therefore, a need still exists for approaches for providing effectiveTSVs, particularly those that allow for firm electrical connectionbetween components and circuits separated by dielectric layers, andthose that avoid voids in via electrodes that can induce connectionfailures between one side of a semiconductor chip to the other side, orbetween chips in a stack of chips.

SUMMARY

In accordance with an exemplary embodiment of the present invention asemiconductor device is provided having a semiconductor substrate and avia electrode. The via electrode includes a first portion on thesubstrate and extends towards the substrate, and a plurality of spikesthat extends from the first portion into the substrate, each of thespikes being spaced apart form one another.

A conductive pad may be on the substrate and contacts the first portion.

The spikes may be cylindrical in shape.

The spikes may be tapered from a smaller diameter at their ends distalfrom the first portion as compared with a diameter of their endsproximal to the first portion.

The first portion may further include a protrusion that extends beyond asurface of the conductive pad distal from the semiconductor substrate.

The first portion may be cylindrical and tapered, with a smallerdiameter at a first portion end distal from the conductive pad ascompared with a first portion end proximal to the conductive pad.

A dielectric layer may be on the substrate, the conductive pad being onthe dielectric layer.

The first portion may extend through the dielectric layer into thesubstrate.

The first portion may extend through the dielectric layer withoutextending into the substrate.

The spikes may extend beyond a surface of the substrate distal from theconductive pad.

The surface of the substrate distal from the conductive pad may includea recess portion exposing a portion of the spikes.

A redistribution line may be connected to the protrusion, theredistribution line extending in a direction substantially parallel witha surface of the semiconductor substrate.

The spikes that extend beyond the surface of the substrate distal fromthe conductive pad may be connected to a protrusion of another viaelectrode in another semiconductor device.

The another semiconductor device may be connected to a module substratehaving conductive bumps by spikes of the via electrode of the anothersemiconductor device penetrating the conductive bumps.

The semiconductor device may be connected to a module substrate havingconductive bumps by the protrusion interfacing with the conductivebumps.

The spikes that extend beyond the bottom surface of the substrate may beconnected to a redistribution line connected to a protrusion of anothervia electrode in another semiconductor device.

In accordance with an exemplary embodiment of the present invention asemiconductor device is provided having a substrate, a first dielectriclayer on the substrate, a conductive pad connected to an interconnectionpattern in the first dielectric layer, and a via electrode having afirst portion and second portion in the substrate, the first portionbeing a cylindrical body and the second portion being a plurality ofspikes that extend from the first portion, each of the spikes beingspaced apart from one another.

The interconnection pattern may include a conductive line and aconductive plug.

The via electrode may be connected to the interconnection pattern by aconductive plug or a conductive line.

The semiconductor device may further include a second dielectric layerincluding a circuit layer between the substrate and the first dielectriclayer. The first portion may extend through the second dielectric layer.

The first dielectric layer may include an interlayer metal dielectriclayer and the second dielectric layer may include an interlayerdielectric layer.

In accordance with an exemplary embodiment of the present invention amethod of forming a semiconductor device is provided. A substrate isformed. A dielectric layer is formed on the substrate. A conductive padis formed on the dielectric layer. A via trench is formed through theconductive pad, the dielectric layer, and a portion of the substrate. Aplurality of spike trenches is formed through a bottom surface of thevia trench and extend into the substrate, each of the spike trenchesbeing spaced apart from each other. A via electrode is formed by fillingthe spike trenches with a first conductive material and filling the viatrench with a second conductive material.

An insulation layer may be formed on the surfaces of the spike trenchesand the via trench.

The first conductive material may be the same as the second conductivematerial.

The first conductive material may include one of W, Al, or polysilicon.

The walls of the spike trenches and the via trench may be lined with abarrier metal prior to filling with the first conductive material andthe second conductive material.

The barrier metal may be one of, or a combination of, Ti, Ta, TiN orTaN.

The second conductive material may be Cu.

A protrusion may be formed on the conductive pad by overfilling the viatrench.

Portions of the via electrode may be exposed by removing portions of thesubstrate opposite the conductive pad.

In accordance with an exemplary embodiment of the present inventionmethod of forming a semiconductor device is provided. A substrate isformed. A via trench is formed into the substrate. A plurality of spiketrenches is formed through a bottom surface of the via trench, furtherextending into the substrate, each of the spike trenches being spacedapart from each other. A via electrode is formed by filling the spiketrenches and the via trench with a conductive material. The top surfaceof the via electrode and the substrate are planarized. A firstdielectric layer is formed on the planarized surface of the substrateand the via electrode. An interconnection pattern is formed in the firstdielectric layer. A conductive pad is formed on the first dielectriclayer.

An insulation layer may be formed on the surfaces of the spike trenchesand the via trench.

The method may further include a second dielectric layer including acircuit layer between the substrate and the first dielectric layer. Thevia electrode may extend through the second dielectric layer.

In accordance with an exemplary embodiment of the present invention amethod of forming a semiconductor device is provided. A substrate isformed. A plurality of spike trenches are formed in the substrate. Thespike trenches are filled with a first conductive material. A dielectriclayer is formed on the substrate. A conductive pad is formed on thedielectric layer. A via trench is formed through the conductive pad andthe dielectric layer. The via trench is filled with a second conductivematerial.

A protrusion may be formed on the conductive pad by overfilling the viatrench.

The first conductive material may include one of W, Al, or polysilicon.

The second conductive material may be Cu.

In accordance with an exemplary embodiment of the present invention amethod of forming a semiconductor chip having a via electrode isprovided. A chip substrate having a chip front surface separated from achip back surface is provided. A pair of via trenches is formed betweenthe chip front surface and the chip back surface, a first trench of thepair extending partially into the chip substrate, a second trench of thepair extending from the first trench further into the chip substrate,the first trench having a larger diameter than the second trench. Thepair of via trenches is filled with electrically conductive material toform the via electrode.

A dielectric layer may be formed on the chip front surface. A conductivepad may be formed on the dielectric layer. A protrusion may be formed onthe conductive pad, the protrusion being electrically coupled to the viaelectrode.

A redistribution circuit line may be electrically coupled to theprotrusion such that via electrode is electrically connectable to otherdevices.

The pair of via trenches may extend from the chip front surface to thechip back surface.

At least one of the pair of via trenches may taper in diameter from thechip front surface toward the chip back surface.

The pair of via trenches may be formed by forming the second trench tohave a plurality of trench spikes that extend from the first trench.

The trench spikes may extend beyond the chip back surface.

In accordance with an exemplary embodiment of the present inventionmethod of stacking a pair of semiconductor chips having via electrodesis provided. Each of the pair of semiconductor chips is formed by:providing a chip substrate having a chip front surface separated from achip back surface, forming a pair of via trenches between the chip frontsurface and the chip back surface, a first trench of the pair extendingpartially into the chip substrate, a second trench of the pair extendingfrom the first trench further into the chip substrate, the first trenchhaving a larger diameter than the second trench, the second trenchhaving a plurality of trench spikes that extend from the first trenchbeyond the chip back surface, filling the pair of via trenches withelectrically conductive material to provide a via electrode, forming adielectric layer on the chip front surface, forming a conductive pad onthe dielectric layer, forming a protrusion on the conductive pad, theprotrusion being electrically coupled to the via electrode, and forminga conductive bump on the protrusion of one of the pair. An adhesive isapplied on the dielectric layer and the conductive pad of the one of thepair for adhering the dielectric layer and the conductive pad of the oneof the pair to the chip back surface of the other of the pair. The pairof semiconductor chips is pressed together such that the spikes of theother of the pair penetrate the conductive bump of the one of the pairand the adhesive contacts the chip back surface of the other of thepair.

In accordance with an exemplary embodiment of the present invention anelectronic subsystem including a host coupled to a memory system havinga memory controller coupled to a memory device is provided. The memorydevice includes a conductive pad on a semiconductor substrate and a viaelectrode. The via electrode includes a first portion contacting theconductive pad and extending towards the substrate and a plurality ofspikes that extend from the first portion further into the substrate.

The host may be a mobile device or a processing device having aprocessor.

The electronic subsystem may further include a wireless interface forcommunicating with a cellular device.

The electronic subsystem may further include a connector for removablyconnecting to a host system. The host system may be one of a personalcomputer, notebook computer, hand held computing device, camera, oraudio reproducing device.

The wireless interface may communicate using a communication interfaceprotocol of a third generation communication system, including one ofcode division multiple access (CDMA), global system for mobilecommunications (GSM), north American digital cellular (NADC),extended-time division multiple access (E-TDMA), wide band code divisionmultiple access (WCDMA), or CDMA2000.

In accordance with an exemplary embodiment of the present invention anelectronic subsystem is provided having a printed circuit boardsupporting a memory unit, a device interface unit and an electricalconnector, the memory unit having a memory that has memory cellsarranged on the printed circuit board, the device interface unit beingelectrically connected to the memory unit and to the electricalconnector through the printed circuit board, at least one of the memoryunit and device interface unit comprising a semiconductor device. Thesemiconductor device includes a conductive pad on a semiconductorsubstrate and a via electrode. The via electrode includes a firstportion contacting the conductive pad and extending towards thesubstrate and a plurality of spikes that extend from the first portionfurther into the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be more clearlyunderstood from the following detailed description taken in conjunctionwith the following accompanying drawings.

FIG. 1 a shows a plan view of a semiconductor chip.

FIG. 1 b is a cross sectional view showing a portion of thesemiconductor chip.

FIG. 1 c is a perspective view showing via electrode 150 of thesemiconductor chip.

FIG. 2 is a cross sectional view showing a portion of a chip accordingto an exemplary embodiment which is a variation of the exemplaryembodiment depicted in FIG. 1 b.

FIG. 3 is a cross sectional view showing a portion of a chip accordingto an exemplary embodiment which is another variation of the exemplaryembodiment depicted in FIG. 1 b.

FIG. 4 is a cross sectional view showing an exemplary embodiment ofportion of a chip which is still another variation of the exemplaryembodiment depicted in FIG. 1 b.

FIG. 5 is a cross sectional view showing an exemplary embodiment whichis a variation of the embodiment depicted in FIG. 4.

FIG. 6 is a cross sectional view showing an exemplary embodiment whichis still another variation of the embodiment depicted in FIG. 1 b.

FIG. 7 is a cross sectional view showing an exemplary embodiment whichis another variation of the embodiment depicted in FIG. 1 b.

FIG. 8 is a cross sectional view showing an exemplary embodiment whichis yet another variation of the embodiment depicted in FIG. 1 b.

FIG. 9 is an alternative to the exemplary embodiment depicted in FIG. 8.

FIG. 10 is a cross sectional view showing an exemplary embodiment of astack module.

FIG. 11 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the exemplary embodiment depictedin FIG. 10.

FIG. 12 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the embodiments depicted in FIGS.10 and 11.

FIG. 13 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the embodiment depicted in FIG. 11.

FIGS. 14, 15 and 16 show exemplary embodiments of electronic subsystemsin accordance with the present invention.

FIGS. 17 a, 17 b, 17 c, 17 d, 17 e, 17 f and 17 g are cross sectionalviews showing an exemplary embodiment of a method for forming theexemplary embodiment depicted in FIG. 8.

FIGS. 18 a and 18 b are cross sectional views showing an exemplaryembodiment of a method for forming the exemplary embodiments of thestack modules depicted in FIGS. 10 or 11.

FIGS. 19 a, 19 b, 19 c and 19 d are cross sectional views showing anexemplary embodiment of a method of forming the chips depicted in FIG. 4or 5 and is a variation of the embodiment depicted in FIGS. 17 a-17 g.

FIGS. 20 a, 20 b, 20 c and 20 d are cross sectional views showing anexemplary embodiment of a method of forming the chip depicted in FIG. 6.

FIGS. 21 a, 21 b and 21 c are cross sectional views of an exemplaryembodiment which is a variation of the embodiment depicted in FIGS. 17a-17 g.

FIG. 22 is a cross sectional view showing an exemplary embodiment ofportion of a chip which is still another variation of the exemplaryembodiment depicted in FIG. 1 b.

FIG. 23 is a cross sectional view showing an interposer device accordingto an exemplary embodiment.

FIG. 24 is a cross sectional view showing an interposer device accordingto another exemplary embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The exemplary embodiments will now be described more fully hereinafterwith reference to the accompanying drawings, in which embodiments areshown. These examples, however, may be embodied in many different formsand should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope. In thedrawings, the thicknesses of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout.

It will be understood that when a layer or element is referred to asbeing “on” another layer or element, it can be directly on the otherlayer or element, or intervening layers may also be present. Further, itwill be understood that when a layer is referred to as being “under”another layer or element, it can be directly under the layer or element,or one or more intervening layers or elements may also be present. Inaddition, it will be understood that when a layer or an element isreferred to as being “between” two layers or elements, it can be theonly layer between the two layers or elements, or one or moreintervening layers or elements may also be present.

It will be understood that the order in which the steps of eachfabrication method according to an exemplary embodiment of the presentinvention disclosed in this disclosure are performed is not restrictedto those set forth herein, unless specifically mentioned otherwise.Accordingly, the order in which the steps of each fabrication methodaccording to an exemplary embodiment of the present invention disclosedin this disclosure are performed can be varied.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the exemplary embodiments.

Spatially relative terms, such as “beneath”, “below”, “bottom”, “lower”,“above”, “top”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”other elements or features would then be oriented “above” the otherelements or features. Thus, the exemplary term “below” can encompassboth an orientation of above and below. The device may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein interpreted accordingly. Also, as usedherein, “vertical” refers to a direction that is substantiallyorthogonal to a horizontal direction.

Example embodiments are described herein with reference to cross-sectionillustrations that are schematic illustrations of idealized embodiments(and intermediate structures). As such, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe present invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the exemplary embodiments of thepresent invention belong. It will be further understood that terms, suchas those defined in commonly used dictionaries, should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthe relevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

Referring now to FIGS. 1 a, 1 b and 1 c an exemplary embodiment of thepresent invention is shown. FIG. 1 a shows a plan view of asemiconductor chip. FIG. 1 b is a cross sectional view showing a portionof the semiconductor chip. FIG. 1 c is a perspective view showing a viaelectrode of the semiconductor chip.

As seen in FIGS. 1 a and 1 b, at least one via electrode 150 is formedpassing through conductive pad 130 and a dielectric layer 120 andextending into substrate 110. Via electrode 150 includes a protrusionpart 156 formed on conductive pad 130 and being electrically connectedto a top of conductive pad 130 exposed from the dielectric 120. Bodypart 154 passes through conductive pad 130 and the dielectric layer 120and extends into substrate 110 directly under protrusion part 156. Spikepart 152 extends into substrate 110 directly under body part 154. Viaelectrode 150 may be formed in a single body such that spike part 152,body part 154 and protrusion part 154 are connected to each other. Bodypart 154 and spike part 152 are electrically insulated from substrate110, the dielectric layer 120 and conductive pad 130 by spacerinsulation layer 140.

As an alternative example, an upper portion of a sidewall of body part154 may contact a sidewall of conductive pad 130 by removing spacerinsulation layer 140 adjacent to the sidewall of conductive pad 130.Spike part 152 may have at least two, and in an exemplary embodimentthree, spike elements, the spike elements becoming narrow in diameter asthey extend further away from conductive pad 130. Each spike element mayhave a smaller diameter than the diameter of body part 154.Additionally, spike part 152, which is used as a multi-prong contactterminal of via electrode 150, is exposed from a backside surface ofsubstrate 110 by removing the backside of the substrate at apredetermined thickness, thereby to be able to combine the chip withanother device by penetrating the exposed portion of spike part 152 intoa portion of the device like a fork. As such, the exemplary embodimentof the present invention can provide high connectability.

FIG. 2 is a cross sectional view showing a portion of a chip accordingto an exemplary embodiment which is a variation of the exemplaryembodiment depicted in FIG. 1 b wherein the spike elements do not taperin diameter. Via electrode 150 a includes protrusion part 156, body part154 and spike part 152 a. In this embodiment, each spike element ofspike part 152 a is of a cylindrical shape having the same spike elementthickness.

FIG. 3 is a cross sectional view showing a portion of a chip accordingto an exemplary embodiment which is another variation of the exemplaryembodiment depicted in FIG. 1 b wherein the body part tapers indiameter. Via electrode 150 b includes protrusion part 156, body part154 b and spike part 152. Both body part 154 b and spike part 152 becomenarrow in their diameters as they extend further away from conductivepad 130.

FIG. 4 is a cross sectional view showing an exemplary embodiment of aportion of a chip which is still another variation of the exemplaryembodiment depicted in FIG. 1 b wherein an interconnection pattern isincluded in the dielectric layer 120, which in an exemplary embodimentis an interlayer metal dielectric layer. Via electrode 150 c includesbody part 154 c and spike part 152. Body part 154 c extends intosubstrate 110 from a front side thereof (top as viewed in FIG. 4)without passing through conductive pad 130 and the dielectric layer 120but is electrically connected to conductive pad 130 using aninterconnection pattern 125 having interconnection lines 124 and plugpatterns 122.

FIG. 5 is a cross sectional view showing an exemplary embodiment whichis a variation of the embodiment depicted in FIG. 4 wherein the bodypart extends into the interlayer dielectric layer. Via electrode 150 dincludes body part 154 d and spike part 152. Unlike body part 154 c inFIG. 4, body part 154 d extends into interlayer dielectric layer 120 abut does not extend into interlayer metal dielectric layer 120 b. Thatis, body part 154 d extends into substrate 110 directly under frombottommost interconnection line 124 a through the interlayer dielectriclayer 120 a. Interlayer dielectric layer 120 a includes circuit layer115, which may provide for a capacitor in DRAM, cell transistor, bitline in Flash memory, or other circuit elements or interconnectionlines. In other exemplary embodiments interlayer metal dielectric layer120 b may also include the interconnection pattern 125 havinginterconnection lines 124 and plug pattern 122.

FIG. 6 is a cross sectional view showing an exemplary embodiment whichis still another variation of the embodiment depicted in FIG. 1 bwherein the body part does not extend into the substrate. Via electrode150 e includes protrusion part 156, body part 154 e and spike part 152e. Body part 154 e passes through conductive pad 130 extending until thefront side surface of substrate 110 and spike part 152 e extends intosubstrate 110 from the front side surface of substrate 110.

FIG. 7 is a cross sectional view showing an exemplary embodiment whichis another variation of the embodiment depicted in FIG. 1 b wherein aredistribution line is connected to the protrusion part. Via electrode150 further includes redistribution line 158 connected to protrusionpart 156, and when there is a connection between the chip and otherdevices, particularly when the other devices have a different size ascompared with the chip, redistribution line 158 acts as a connectionterminal that connects the chip to the other device. Redistribution line158 may similarly be connected to protrusion part 156 previously shownin FIGS. 2, 3, and 6 and as will be shown in FIGS. 8 and 9 below.Redistribution line 158 may also be directly connected to conductive pad130 shown in FIGS. 4 and 5.

FIG. 8 is a cross sectional view showing an exemplary embodiment whichis yet another variation of the embodiment depicted in FIG. 1 b whereinthe spikes extend beyond the substrate. Via electrode 150 passes throughsubstrate 110. That is, spike part 152 of via electrode 150 is exposedfrom the backside surface of substrate 110 (bottom as seen in FIG. 9)and/or protrudes from substrate 110. In this case, spacer insulationlayer 140 may be removed adjacent the exposed or protruding spike part152. The exposed or protruding via electrode structure is alsoapplicable to via electrodes 150 a, 150 b, 150 c, 150 d, 150 e as shownin FIGS. 2-7.

Referring now to FIG. 9, as an alternative to the exemplary embodimentdepicted in FIG. 8, trench 108 may be formed which additionally exposessidewalls of a lower portion of each spike part 152 by recessing aportion of the backside of substrate 110 adjacent to spike part 152.Spacer insulation layer 140 is also removed within the trench area.

FIG. 10 is a cross sectional view showing an exemplary embodiment of astack module. The stack module provides for multiple chips by stackingthe chips together and whose via electrodes interconnect adjacent chips.In FIG. 10 three semiconductor chips 210, 220, 230 are sequentiallystacked each other using conductive bumps 170 a. However, this is justan exemplary embodiment. As such, there is no limitation in the numberof chips that can be stacked. The chips may be at least one of the chipsin FIGS. 8 and 9 and also the chips including via electrodes 150 a, 150b, 150 c, 150 d, 150 e in FIGS. 2-6 if they have their spike partsexposed from substrate 110. In the embodiment of FIG. 10 the chips havethe same size as each other. The via electrode 150 of chip 230 isconnected to the conductive bump 170 a of chip 220 by penetrating spikeparts 152 of via electrode 150 of chip 230 into the conductive bump 170a of chip 220. The cylindrical structure of the spike parts 152 providesincreased contact area between the spike parts 152 and the conductivebump 170 a. Similarly, the via electrode 150 of chip 220 is connected tothe conductive bump 170 a of chips 210 by penetrating spike parts 152 ofvia electrode 150 of chip 220 into the conductive bump 170 a of chip210.

FIG. 11 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the exemplary embodiment depictedin FIG. 10 wherein one of the semiconductor chips is stacked on a modulesubstrate. Chips 210, 220, 230 are stacked together on module substrate205, which may include, for example, a PCB or tape type substrate. Spikepart 152 of chip 210 penetrates into conductive bump 170 a formed onmodule substrate 205. An adhesive layer 180 is further provided betweenchips 210, 220, 230. Solder ball 250 is further provided on the backsideof module substrate 205 opposite to the front side on which conductivebump 170 a is formed.

FIG. 12 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the embodiments depicted in FIGS.10 and 11 wherein the direction of the via electrodes is reversed. Eachprotrusion part 156 of via electrodes 150 of chips 210, 220, 230 in FIG.11 is turned over facing conductive bump 170 a formed on modulesubstrate 205. Protrusion part 156 of chip 210 a is then connected ontoconductive bump 170 a of module substrate 205.

FIG. 13 is a cross sectional view showing an exemplary embodiment of astack module which is a variation of the embodiment depicted in FIG. 11.As compared with FIG. 11, chips 210 b, 220 b, 230 b have the differentsizes from each other and the chips 220 b, 210 b, include redistributionlines 158 as depicted in FIG. 7. For example, at least one of the chips210 b, 220 b, 230 b may be the same type device or a different type ofdevice having sizes different from each other such that the chipsconfigure a System In Package (SIP). Via electrodes 150 of chips 210 b,220 b, 230 b may not be aligned with each other along the verticaldirection. Via electrode 150 of chip 230 b extends under substrate 110of chip 230 b and connects to redistribution line 158 of chip 220 bthrough a conductive bump 170 a. Also, via electrode 150 of chip 220 bextends under substrate 110 of chip 220 b and connects to redistributionline 158 of chip 210 b through conductive bump 170 a.

Those skilled in the art will appreciate that if the exemplaryembodiments depicted in FIGS. 10-13 were modified such that the trench108 as shown in FIG. 9 is included in substrates 110, additional contactarea between spike parts 152 and conductive bump 170 a will be providedand add further interconnection strength.

Referring now to FIGS. 14-16, various electronic subsystems are depictedwhich implement at least one of the exemplary embodiments describedabove.

FIG. 14 shows an electronic subsystem which includes a semiconductordevice according to at least one exemplary embodiment of the presentinvention. Electronic subsystem 700 includes a memory controller 720 anda memory 710, either of which may have a structure according to at leastone exemplary embodiment of the present invention. The memory controller720 controls the memory device 710 to read or write data from/into thememory 710 in response to a read/write request of a host 730. The memorycontroller 720 may include an address mapping table for mapping anaddress provided from the host 730 (e.g., mobile devices or computersystems) into a physical address of the memory device 710. By usingsemiconductor devices in accordance with at least one exemplaryembodiment of the present invention reliable interconnection betweenlayers of semiconductor chips in the memory controller and/or memory canresult in better overall interconnection reliability of the electronicsubsystem.

Referring to FIG. 15, an electronic subsystem including a semiconductordevice according to at least one exemplary embodiment of the presentinvention will now be described. Electronic subsystem 800 may be used ina wireless communication device (e.g., a personal digital assistant, alaptop computer, a portable computer, a web tablet, a wirelesstelephone, a mobile phone and/or a wireless digital music player.) or inany device capable of transmitting and/or receiving information viawireless environments.

The electronic subsystem 800 includes a controller 810, an input/output(I/O) device 820 (e.g., a keypad, a keyboard, and a display), a memory830, and a wireless interface 840, each device being coupled to acommunication bus 850 and may have a structure according to at least oneexemplary embodiment of the present invention. The controller 810 mayinclude at least one of a microprocessor, a digital signal processor, ora similar processing device. The memory 830 may be used to storecommands executed by the controller 810, for example. The memory 830 maybe used to store user data. The electronic system 800 may utilize thewireless interface 840 to transmit/receive data via a wirelesscommunication network. For example, the wireless interface 840 mayinclude an antenna and/or a wireless transceiver. The electronic system800 according to exemplary embodiments may be used in a communicationinterface protocol of a third generation communication system, e.g.,code division multiple access (CDMA), global system for mobilecommunications (GSM), north American digital cellular (NADC),extended-time division multiple access (E-TDMA) and/or wide band codedivision multiple access (WCDMA), CDMA2000. By using semiconductordevices in accordance with at least one exemplary embodiment of thepresent invention reliable interconnection between layers ofsemiconductor chips in the controller, I/O device, memory and/orwireless interface can result in better overall interconnectionreliability of the electronic subsystem.

Referring to FIG. 16, an electronic subsystem including a semiconductordevice according to at least one exemplary embodiment of the presentinvention will now be described. Electronic subsystem 900 may be amodular memory device and includes a printed circuit board 920. Theprinted circuit board 920 may form one of the external surfaces of themodular memory device 900. The printed circuit board 920 may support amemory unit 930, a device interface unit 940, and an electricalconnector 910.

The memory unit 930 may have a various data storage structures,including at least one exemplary embodiment of the present invention,and may include a three-dimensional memory array and may be connected toa memory array controller. The memory array may include the appropriatenumber of memory cells arranged in a three-dimensional lattice on theprinted circuit board 920. The device interface unit 940 may be formedon a separated substrate such that the device interface unit 940 may beelectrically connected to the memory unit 930 and the electricalconnector 910 through the printed circuit board 920. Additionally, thememory unit 930 and the device interface unit 940 may be directlymounted on the printed circuit board 920. The device interface unit 940may include components necessary for generating voltages, clockfrequencies, and protocol logic. By using semiconductor devices inaccordance with at least one exemplary embodiment of the presentinvention reliable interconnection between layers of semiconductor chipsin the memory unit can result in better overall interconnectionreliability of the electronic subsystem.

FIGS. 17 a-17 g are cross sectional views showing an exemplaryembodiment of a method for forming the exemplary embodiment depicted inFIG. 8. Referring first to FIG. 17 a, via trench 133 is formed throughconductive pad 130, dielectric layer 120 and a portion of substrate 110using laser drilling and/or a dry etch using a conventional photo maskpattern.

As seen in FIG. 17 b, spike trench 136 is formed extending intosubstrate 110 from the bottom surface of via trench 133. Spike trench136 does not pass through substrate 110 nor does it extend to thebackside surface of substrate 110. Spike trench 136 may be formed byetching the exposed substrate directly under via trench 133 using aconventional photo mask pattern. In an exemplary embodiment, each fingerof spike trench 136 has a diameter of about 5 μm and via trench 133 hasa diameter of about 30-35 μm. Alternatively, each finger of spike trench136 having a diameter of about 10 μm may be formed using the laserdrilling having a beam size of about 10 μm in case of via trench 133having the diameter of about 30-35 m. A depth of via trench 133 may bealmost the same as the depth of spike trench 136 or even larger than thedepth of spike trench 136 in view of the needed filling characteristics.Because the depth of via trench 133 can be shorter than the depth of aconventional via trench having no spike trench 136, the aspect ratio ofvia trench 133 can become smaller than the aspect ratio of theconventional via trench. As such, the smaller aspect ratio helps preventa void from being formed during filling for a TSV.

As seen in FIG. 17 c, spacer insulation layer 140 is then formed alongthe surface of via trench 133 and spike trench 136, and the innersurface of conductive pad 130.

As seen in FIG. 17 d, via electrode 150 is formed filling spike trench136 and via trench 133 with conductive material and extending ontoconductive pad 130. Those exemplary embodiments having tapered diametertrenches make it easier and less time consuming to fill the conductivematerial.

As depicted in FIG. 17 e, spike part 152 may have a first conductivelayer 163 made of W, Al or poly silicon, and body part 154 andprotrusion part 156 may include both the first conductive layer 163 andsecond conductive layer 166 made of Cu using conventional platingmethods. When using Cu as a material of spike part 152, Cu exposed fromthe backside surface of substrate 110 may act as a contamination source.But, in some cases, first and second conductive layers 163, 166 mayinclude Cu, W, Al, or poly silicon.

First conductive layer 163 further extends along the sidewall and bottomregion of via trench 133. A barrier metal may be further formed underfirst and second conductive layers 163, 166. The barrier metal may bemade of at least one of Ti, Ta, TiN or TaN.

As seen in FIG. 17 f, a bottom portion of spike part 152 is exposed fromthe backside of substrate 110 by removing the backside portion ofsubstrate 110 at a predetermined thickness using an etch back and/orchemical-mechanical polishing (CMP), followed by removing the bottomportion of spacer insulation layer 140, so that via electrode 150 maypass through substrate 110.

As seen in FIG. 17 g, by removing using an anisotropic and/or isotropicetch even more of the backside of substrate 110, the bottom portion ofspike part 152 including the sidewall thereof can protrude from thebackside of substrate 110. At this time, a portion of spacer insulationlayer 140 exposed adjacent the sidewall of spike part 152 is selectivelyremoved.

FIGS. 17 a and 17 b are cross sectional views showing an exemplaryembodiment of a method for forming the exemplary embodiments of thestack modules depicted in FIGS. 10 or 11, but would also applicable tothe exemplary embodiments depicted in FIGS. 17 and 17.

Referring first to FIG. 18 a, on each protrusion part 156 of viaelectrodes 150 of chips 210, 220 is formed conductive bump 170, and oneach backside surface of chips 210, 220 is formed adhesive layer 180.After stacking these chips 210, 220 to each other, chips 210, 220 arecompressed to each other by pressure.

As seen in FIG. 18 b, chips 210, 220 are attached each other by adhesivelayer 180 and spike part 152 of chip 220 penetrating into compressedconductive bump 170 a of chip 210 by the pressure. Optionally, byreflowing conductive bump 170 a, the connection strength between spikepart 152 and conductive bump 170 a may be increased even more.

FIGS. 19 a-19 d are cross sectional views showing an exemplaryembodiment of a method of forming the chips depicted in FIG. 4 or 5 andis a variation of the method depicted in FIGS. 17 a-17 e whereininterconnection lines are included.

Referring first to FIG. 19 a, before forming the dielectric layer 120and conductive pad 130, via trench 133 c is formed extending intosubstrate 110 from the front surface thereof. Spike trench 136 extendsinto substrate 110 directly under the bottom surface of via trench 133c.

As seen in FIG. 19 b, via electrode 150 c consisting of body part 154 cand spike part 152, without a protrusion part, is formed in via trench133 c and spike part 136. Via electrode 150 c may be formed by filling aconductive layer in these trenches and then, planarizing the conductivelayer until the front surface of substrate 110 is exposed, but notpatterning as in FIG. 17 d.

Referring to FIG. 19 c, the dielectric layer 120, for example, aninterlayer metal dielectric layer, interconnection pattern 125, whichincludes interconnection lines 124 and plug patterns 122, and conductivepad 130 are sequentially formed on the front surface of substrate 110over via electrode 150 c as shown in FIGS. 4 or 5.

As seen in FIG. 19 d, by removing a backside portion of substrate 110, abottom portion of spike part 152 is exposed protruding from the backsidesurface of substrate 110.

FIGS. 20 a-20 d are cross sectional views showing an exemplaryembodiment of a method of forming the chip depicted in FIG. 6. Referringto FIG. 20 a, spike trench 136 e is formed extending into substrate 110from the front surface of substrate 110.

As seen in FIG. 20 b, spike part 152 e is formed by filling a conductivelayer into spike trench 136 e.

As seen in FIG. 20 c, dielectric layer 120 and conductive pad 130 aresequentially formed directly over spike part 152 e formed into substrate110. Via trench 133 e is then formed passing through conductive pad 130and the dielectric layer 120 and exposing spike part 152 e.

Referring now to FIG. 20 d, via electrode 150 e, including body part 154filling via trench 133 e and protrusion part 156 protruding fromconductive pad 130, are formed contacting spike part 152 e. The bottomportion of via electrode 150 e protrudes from the backside surface ofsubstrate 110.

FIGS. 21 a-21 c are cross sectional views of an exemplary embodimentwhich is a variation of the embodiment depicted in FIGS. 17 a-17 g. Thevariation includes, after forming via trench 133, forming spike trench136 by etching or drilling from the backside of substrate 110 toward thebottom surface of via trench 133. The shape of spike trench 136 may be acylinder type, a tapered type or a reverse tapered type.

FIG. 22 is a cross sectional view showing an exemplary embodiment ofportion of a chip which is still another variation of the exemplaryembodiment depicted in FIG. 1 b.

Referring to FIG. 22, at least one via electrode 250 is formed passingthrough the conductive pad 130, the dielectric layer 120 and thesubstrate 110. The via electrode 250 includes a protrusion part 256formed on the substrate 110, for example, a backside surface thereofopposite to the conductive pad 130. The body part 254 passes through thesubstrate 110 and extends into the dielectric layer 120 directly on theprotrusion part 256. The spike part 252 is formed passing through thedielectric layer 120 and the conductive pad 130 directly on the bodypart 254 and being connected to a conductive pad 130. The spike part 252may protrude upwardly from the conductive pad 130. In some embodiments,a top portion of the spike part 252 may be aligned with a top portion ofthe conductive pad 130. The via electrode 250 may be formed in a singlebody such that spike part 252, body part 254 and protrusion part 254 areconnected to each other. The body part 254 and the spike part 252 areelectrically insulated from the substrate 110, the dielectric layer 120and the conductive pad 130 by spacer insulation layer 240. The body part254 may be formed only in the substrate 110 or only in the dielectriclayer 120. The protrusion part 154 may be omitted.

FIG. 23 is a cross sectional view showing an interposer device accordingto an exemplary embodiment.

Referring to FIG. 23, a substrate 310 is provided. A first wiringpattern 332 is provided on the substrate 310. A second wiring pattern336 is provided on the first wiring pattern 332. The second wiringpattern 336 is connected to the first wiring pattern 332 throughconductive plugs 334 passing through a dielectric layer 320. At leastone via electrode 350 is provided to extend through the semiconductorsubstrate vertically and is electrically connected to the second wiringpattern 336. A spacer insulation layer 340 is provided between the viaelectrode 350 and the substrate 310. The via electrode 350 includes abody part 354 and a spike part 352. The body part 354 passes through thedielectric layer 320 directly under the second wiring pattern 336 andextends into the substrate 310. The spike part 352 passes through thesubstrate 310 directly under the body part 354. The body part 354 andthe spike part 352 are electrically connected each other.

The interposer device could be interposed between stacked chips, betweenstacked packages or between stacked chip and package to electricallyconnect chip to chip, package to package or chip to package. FIG. 24 isa cross sectional view showing an interposer device according to anotherexemplary embodiment. The interposer device is similar to the interposerdevice of FIG. 23 and thus repeated explanations are omitted.

Referring to FIG. 24, the via electrode 350 includes a body part 354, aprotrusion part 356 and a spike part 352. The body part 354 passesthrough the dielectric layer 320 and the conductive pad 332 directlyunder the protrusion part 356 and extends into the substrate 310.

In accordance with exemplary embodiments of the present invention, whena chip is connected to other device, a spike part of the chip is firmlycombined with the device penetrating into a portion of the device. Inthe case of chip stack module, the chips are firmly combined with eachother by a penetration of the spike part into a conductive bump. Assuch, a void generation in a via electrode is prevented and connectionreliability may be improved.

Although the present invention has been described in connection withexemplary embodiments illustrated in the accompanying drawings, it isnot limited thereto. Persons with skill in the art will recognize thatembodiments of the present invention may be applied to other types ofmemory devices. The above-disclosed subject matter is to be consideredillustrative, and not restrictive, and the appended claims are intendedto cover all such modifications, enhancements, and other embodiments,which fall within the true spirit and scope of the present invention.

1-22. (canceled)
 22. A method of forming a semiconductor device,comprising: forming a substrate; forming a dielectric layer on thesubstrate; forming a conductive pad on the dielectric layer; forming avia trench through the conductive pad, the dielectric layer, and aportion of the substrate; and forming a plurality of spike trenchesthrough a bottom surface of the via trench and extending into thesubstrate, each of the spike trenches being spaced apart from eachother; and forming a via electrode by filling the spike trenches with afirst conductive material and filling the via trench with a secondconductive material.
 23. The method of claim 22, further comprisingforming an insulation layer on the surfaces of the spike trenches andthe via trench.
 24. The method of claim 22, wherein the first conductivematerial is the same as the second conductive material.
 25. The methodof claim 22, wherein the first conductive material comprises one of W,Al, or polysilicon.
 26. The method of claim 22, further comprisinglining the walls of the spike trenches and the via trench with a barriermetal prior to filling with the first conductive material and the secondconductive material.
 27. The method of claim 26, wherein the barriermetal comprises one of, or a combination of, Ti, Ta, TiN or TaN.
 28. Themethod of claim 22, wherein the second conductive material is Cu. 29.The method of claim 22, including forming a protrusion on the conductivepad by overfilling the via trench.
 30. The method of claim 22, furtherincluding exposing portions of the via electrode by removing portions ofthe substrate opposite the conductive pad.
 31. A method of forming asemiconductor device, comprising: forming a substrate; forming a viatrench into the substrate; forming a plurality of spike trenches througha bottom surface of the via trench, further extending into thesubstrate, each of the spike trenches being spaced apart from eachother; forming a via electrode by filling the spike trenches and the viatrench with a conductive material; planarizing the top surface of thevia electrode and the substrate; forming a first dielectric layer on theplanarized surface of the substrate and the via electrode; forming aninterconnection pattern in the first dielectric layer; and forming aconductive pad on the first dielectric layer.
 32. The method of claim31, further comprising forming an insulation layer on the surfaces ofthe spike trenches and the via trench
 33. The method of claim 31,further comprising a second dielectric layer including a circuit layerbetween the substrate and the first dielectric layer, and wherein thevia electrode extends through the second dielectric layer.
 34. A methodof forming a semiconductor device, comprising: forming a substrate;forming a plurality of spike trenches in the substrate; filling thespike trenches with a first conductive material; forming a dielectriclayer on the substrate; forming a conductive pad on the dielectriclayer; forming a via trench through the conductive pad and thedielectric layer; and filling the via trench with a second conductivematerial.
 35. The method of claim 34, further including forming aprotrusion on the conductive pad by overfilling the via trench.
 36. Themethod of claim 34, wherein the first conductive material comprises oneof W, Al, or polysilicon.
 37. The method of claim 34, wherein the secondconductive material is Cu.
 38. A method of forming a semiconductor chiphaving a via electrode, comprising: providing a chip substrate having achip front surface separated from a chip back surface; forming a pair ofvia trenches between the chip front surface and the chip back surface, afirst trench of the pair extending partially into the chip substrate, asecond trench of the pair extending from the first trench further intothe chip substrate, the first trench having a larger diameter than thesecond trench, and filling the pair of via trenches with electricallyconductive material to form the via electrode.
 39. The method of claim38, further comprising: forming a dielectric layer on the chip frontsurface, forming a conductive pad on the dielectric layer, forming aprotrusion on the conductive pad, the protrusion being electricallycoupled to the via electrode.
 40. The method of claim 39, furthercomprising electrically coupling a redistribution circuit line to theprotrusion such that via electrode is electrically connectable to otherdevices.
 41. The method of claim 38, wherein the pair of via trenchesextend from the chip front surface to the chip back surface.
 42. Themethod of claim 38, wherein at least one of the pair of via trenchestaper in diameter from the chip front surface toward the chip backsurface.
 43. The method of claim 38, wherein forming the pair of viatrenches comprises forming the second trench to have a plurality oftrench spikes that extend from the first trench.
 44. The method of claim43, wherein the trench spikes extend beyond the chip back surface.
 45. Amethod of stacking a pair of semiconductor chips having via electrodes,comprising: forming each of the pair of semiconductor chips by:providing a chip substrate having a chip front surface separated from achip back surface; forming a pair of via trenches between the chip frontsurface and the chip back surface, a first trench of the pair extendingpartially into the chip substrate, a second trench of the pair extendingfrom the first trench further into the chip substrate, the first trenchhaving a larger diameter than the second trench, the second trenchhaving a plurality of trench spikes that extend from the first trenchbeyond the chip back surface, filling the pair of via trenches withelectrically conductive material to provide a via electrode, forming adielectric layer on the chip front surface, forming a conductive pad onthe dielectric layer, forming a protrusion on the conductive pad, theprotrusion being electrically coupled to the via electrode, and forminga conductive bump on the protrusion of one of the pair, applying anadhesive on the dielectric layer and the conductive pad of the one ofthe pair for adhering the dielectric layer and the conductive pad of theone of the pair to the chip back surface of the other of the pair; andpressing the pair of semiconductor chips together such that the spikesof the other of the pair penetrate the conductive bump of the one of thepair and the adhesive contacts the chip back surface of the other of thepair. 46-51. (canceled)